主讲人：Vasilis F. Pavlidis
Energy efficiency has become a predominant objective in the design of integrated circuits and systems. Three-dimensional (3-D) integration supports enhanced power data and memory transfers due to the proximity of circuit components. However, the physical proximity offers limited power gains. In this talk, I will demonstrate how voltage scaling – a standard low power method for integrated circuits – can be applied in the context of multi-tier circuits demonstrating significant power savings without compromising the system performance. An appropriate design flow to underpin the discussed approach based mainly on commercial EDA tools is also discussed.
Power (and performance) also depends upon the developed temperatures within a circuit. In 3-D ICs, higher temperatures are expected due to greater power densities. Accurately predicting the temperature within a 3-D circuit is an important task. We have recently released an open-source thermal analysis tool that can provide fast thermal map of 2-D or 3- D circuits at both the block and cell level including, differently from other thermal tools, versatile system structures and the surroundings of the circuit. The features of the tool and some related benchmarks will be presented in the second part of the talk.
Short biography: Vasilis Pavlidis is an Associate Professor in the School of Computer Science at the University of Manchester, UK. He holds an MSc and PhD degree from the University of Rochester, Rochester, NY, obtained in 2003 and 2008, respectively, all in Electrical and Computer Engineering. From 2008 to 2012, he was a post-doctoral researcher at the Integrated Systems Laboratory of EPFL, Switzerland. His research interests are in the area of interconnect modeling and analysis, 3D integration, and other issues related to VLSI design. He is the leading author of the book Three-Dimensional Integrated Circuit Design, (1st and 2nd Editions), also translated in Chinese, and contributor to the software tool, Manchester Thermal Analyzer.